Method of fabricating W/TiN gate for MOSFETS

ABSTRACT

A dielectric layer is etched to form an opening in dielectric layer. A gate oxide layer is formed on semiconductor substrate in said opening. A barrier conductor is formed along the surface of the opening. A metal layer is formed on the barrier conductor and refilled into the opening. A portion of the metal layer and the barrier conductor is removed to form a gate for said transistor. The dielectric layer is removed. The barrier conductor is removed on sidewall of the gate. Lightly doped drain region is formed in the semiconductor substrate. Next, Sidewall spacer is formed on sidewall of the gate. Then, source and drain is formed in the semiconductor substrate by ion implantation using the gate and spacer as masking.

FIELD OF INVENTION

[0001] The present invention relates to a semiconductor device, and morespecifically, to a method of fabricating a metal oxide semiconductorfield effect transistor (MOSFET) for used in deep sub-micron meterrange.

BACKGROUND OF THE INVENTION

[0002] The semiconductor industry has been advanced in an ever briskpace, recently. In order to achieve high performance integrated circuitsor high package density of a wafer, the sizes of semiconductor deviceshave become smaller and smaller than before in the field of Ultra LargeScale Integrated (ULSI) technologies. The semiconductor industry hasbeen advanced to the field of Ultra Large Scale Integrated (ULSI)technologies. The fabrication of the metal-oxide-semiconductortransistor also follows the trend. As the size of the devices is scaleddown, silicon based nano-scale electronics have been attention for theseyears. For example, single-electron-tunneling devices are developed inrecent years.

[0003] Integrated circuits includes more than millions devices in aspecific area of a wafer and electrically connecting structure forconnecting these devices to perform desired function. One of the typicaldevices is metal oxide semiconductor field effect transistor (MOSFET).The MOSFET has been widely, traditionally applied in the semiconductortechnologies. As the trend of the integrated circuits, the fabricationof the MOSFET also meets various issues to fabricate them. The typicallyissue that relates to hot carriers injection is overcame by thedevelopment of lightly doped drain (LDD) structure.

[0004] Further, the requirement of the devices towards high operationspeed and low operation power. For deep sub-micron meter MOS devices,the self-aligned silicide (SALICIDE) contact, ultra-shallow source anddrain junction are used for improving the operation speed and shortchannel effect. In another research by T. Yoshitomi, he develops a highperformance CMOS with good control of short channel effect and silicideresistance. Please see “High Performance 0.15 μm Single Gate Co SalicideCMOS, T. Yoshitomi et al., 1996, Symposium on VLSI Technology Digest ofTechnical papers”. The CoSi₂, NiSi have been used for deep sub-micronhigh speed CMOS due to the low sheet resistance of fine silicide line.However, it is difficult to make ultra-shallow junction and formSALICIDE contact without degrading the device performance.

[0005] The requirement of the ULSI CMOS technology is the need ofdevices operated at low supply voltage and they have high speed. Whenthe supply-voltage is reduced, the threshold voltage needs to be scaleddown to achieve the desired circuit switching speed. IBM has proposedthat CMOS employs non-uniform channel doping profiles and ultra-shallowsource and drain extensions and halos, which can be referenced in “CMOStechnology scaling 0.1 μm and beyond, IBM semiconductor research anddevelopment center, Bijan Davari, 1996, IEDM, 96-555”. For the highperformance case, the threshold voltage is scaled down less than thesupply voltage in order to maintain a reasonable standby current.

[0006] U.S. Pat. No. 6,261,934 which assigned to Texas InstrumentsIncorporated (Dallas, Tex.), entitled “Dry etch process forsmall-geometry metal gates over thin gate dielectric” discloses astructure for semiconductor device. As geometries shrink into the deepsubmicron regime (below 0.5 or 0.35 micron), such buried channels becomevery undesirable. Thus one of the constraints on new gate materials is agood work-function match to the semiconductor used. Titanium nitride isa very promising candidate for gate electrode material. It has a workfunction near the mid-gap point of silicon (4.65 eV) and eliminates gatedepletion effects. However, titanium nitride has a quite highresistivity (120 m.OMEGA.-cm), and therefore needs to be used inconjunction with a material with higher conductivity for lowinterconnect delays to be achieved. For that purpose, tungsten(resistivity of 8 m.OMEGA.-cm) has been used.

SUMMARY OF THE INVENTION

[0007] The method of the present invention includes forming a dielectriclayer on said semiconductor substrate. A dielectric layer is etched toform an opening in dielectric layer. A gate oxide layer is formed onsemiconductor substrate in said opening. A barrier conductor is formedalong the surface of the opening. A metal layer is formed on the barrierconductor and refilled into the opening. A portion of the metal layerand the barrier conductor is removed to form a gate for said transistor.The dielectric layer is removed. The barrier conductor is removed onsidewall of the gate. Lightly doped drain region is formed in thesemiconductor substrate. Next, Sidewall spacer is formed on sidewall ofthe gate. Then, source and drain is formed in the semiconductorsubstrate by ion implantation using the gate and spacer as masking.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The foregoing aspects and many of the attendant advantages ofthis invention will become more readily appreciated as the same becomesbetter understood by reference to the following detailed description,when taken in conjunction with the accompanying drawings, wherein:

[0009]FIG. 1 is a cross section view of a semiconductor waferillustrating the steps of forming a dielectric layer, a barrierconductor and metal layer on a semiconductor substrate according to thepresent invention.

[0010]FIG. 2 is a cross section view of a semiconductor waferillustrating the step of forming a gate structure according to thepresent invention.

[0011]FIG. 3 is a cross section view of a semiconductor waferillustrating the step of removing the dielectric layer according to thepresent invention.

[0012]FIG. 4 is a cross section view of a semiconductor waferillustrating the step of removing the TiN according to the presentinvention.

[0013]FIG. 5 is a cross section view of a semiconductor waferillustrating the step of forming LDD and source and drain according tothe present invention.

[0014]FIG. 6 is a cross section view of a semiconductor waferillustrating another structure according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0015] The present invention proposes a novel method to fabricate a W/Sigate for MOSFETS. In the present invention, the technology can increasethe device performance.

[0016] In a preferred embodiment, a single crystal silicon substrate 2with a <100> crystallographic orientation is provided. Thick field oxide(FOX) regions or shallow trench isolation are formed to provideisolation between devices on the substrate. In a case, the FOX regionscan be formed via lithography and etching steps to etch a siliconnitride-silicon dioxide composition layer. After the photoresist isremoved and wet cleaned, thermal oxidation in steam environment is usedto grow the FOX regions 4 to a thickness of about 3000-8000 angstroms.The FOX regions 4 can be replaced by a plurality of shallow trenchisolations, as well known in the art.

[0017] A first dielectric layer 4 is then formed over the substrate 2using a low-pressure chemical vapor deposition process. In preferredembodiment, the first dielectric layer 4 is formed of oxide, nitride,oxynitride or the combination thereof. Turning to FIG. 1, next, standardlithography and etching steps are used to etch the first dielectriclayer 4 to form an opening 5 for exposing the substrate 2. The gateoxide layer 6 is formed after the step by thermal oxidation. A silicondioxide layer 6 is formed on the top surface of the substrate 2 to serveas a gate oxide of a subsequently formed MOSFET. Typically, the silicondioxide layer 6 is formed in an oxygen ambient at a temperature of about800 to 1100 centigrade degrees. In the embodiment, the thickness of thesilicon dioxide layer 6 is approximately 15-250 angstroms.Alternatively, the oxide layer 6 may be formed using any suitable oxidechemical compositions and procedures, such as chemical vapor deposition.

[0018] Subsequently, a barrier conductor (Titanium nitride) 8 is formedon the first dielectric layer 4 and along the surface of the opening 5,preferably, the barrier conductor 8 is formed of TiN. Then, a metallayer 10 is formed on the barrier conductor 8 and refilled into theopening 5. In a preferred embodiment, the metal layer 10 is formed oftitanium, tungsten, aluminum, or copper.

[0019] Next, a chemical mechanical polishing is used to remove thebarrier conductor 8 and metal layer 10 to the surface of the firstdielectric layer 4 for forming the gate, as shown in FIG. 2.

[0020] Turning to FIG. 3, the first dielectric layer 4 is removed by hotphosphorus, BOE or HF solution depending on the material for forming thefirst dielectric layer 4. An isotropical etching is used to remove theTitanium nitride 8 attached on the tungsten gate 10 as shown in FIG. 4.The plasma-etching recipe may include O₂+C₂F₆. U.S. Pat. No. 6,261,934disclosed the method to etch the Titanium nitride 8. The step may beomitted. If the TiN does not be removed, oblique (titled) angle ionimplantation such as LATIPS (large tilt-angle implanted punch-throughstopper) may be used for forming the LDD.

[0021] Please turn to FIG. 5, lightly doped drain regions 12 are formedby using ion implantation. Next, spacer 14 is formed on the sidewall ofthe gate 10. The step can be achieved by forming a dielectric layer thenetching the layer. Finally, source and drain 16 are created by ionimplantation using the gate 10 and space 14 as the masking.

[0022] Another structure after the sidewall TiN is striped is shown inFIG. 6. It has to be noted that the structure include under cut portion11 under the gate 10. After the spacer is formed, the LDD structure maybe formed by using oblique rotation ion implantation such as LATIPS(large tilt-angle implanted punch-through stopper) technique. The LATIPStransistor employs a large tilt-angle implanted punch-through stopper(LATIPS). This implant forms higher concentration doped regions underthe gate to prevent bulk punch-through.

[0023] As will be understood by persons skilled in the art, theforegoing preferred embodiment of the present invention is illustrativeof the present invention rather than limiting the present invention.Having described the invention in connection with a preferredembodiment, modification will now suggest itself to those skilled in theart. Thus, the invention is not to be limited to this embodiment, butrather the invention is intended to cover various modifications andsimilar arrangements included within the spirit and scope of theappended claims, the scope of which should be accorded the broadestinterpretation so as to encompass all such modifications and similarstructures. While the preferred embodiment of the invention has beenillustrated and described, it will be appreciated that various changescan be made therein without departing from the spirit and scope of theinvention.

What is claimed is:
 1. A method for manufacturing a transistor on asemiconductor substrate, said method comprising the steps of: forming adielectric layer on said semiconductor substrate; etching saiddielectric layer to form an opening in said first dielectric layer;forming a gate oxide layer on said semiconductor substrate in saidopening; forming a barrier conductor along the surface of said opening;forming a metal layer on said barrier conductor and refilled into saidopening; removing a portion of said metal layer and said barrierconductor to form a gate for said transistor; removing said dielectriclayer; stripping said barrier conductor on sidewall of said gate;forming lightly doped drain region is said semiconductor substrate;forming sidewall spacer on sidewall of said gate; and forming source anddrain in said semiconductor substrate by ion implantation using saidgate and spacer as masking.
 2. The method of claim 1, wherein saiddielectric layer comprises silicon oixde, silicon oxynitride or siliconnitride.
 3. The method of claim 1, wherein said barrier conductorcomprises titanium nitride, tungsten, aluminum or copper.
 4. The methodof claim 1, wherein said metal layer comprises titanium.
 5. A method formanufacturing a transistor on a semiconductor substrate, said methodcomprising the steps of: forming a dielectric layer on saidsemiconductor substrate; etching said dielectric layer to form anopening in said first dielectric layer; forming a gate oxide layer onsaid semiconductor substrate in said opening; forming a barrierconductor along the surface of said opening; forming a metal layer onsaid barrier conductor and refilled into said opening; removing aportion of said metal layer and said barrier conductor to form a gatefor said transistor; removing said dielectric layer; forming lightlydoped drain region is said semiconductor substrate by titled angle ionimplantation; forming sidewall spacer on sidewall of said gate; andforming source and drain in said semiconductor substrate by ionimplantation using said gate and spacer as masking.
 6. The method ofclaim 5, wherein said dielectric layer comprises silicon oixde, siliconoxynitride, silicon nitride.
 7. The method of claim 5, wherein saidbarrier conductor comprises titanium nitride, tungsten, aluminum orcopper.
 8. The method of claim 5, wherein said metal layer comprisestitanium.
 9. The method of claim 5, wherein said titled angle ionimplantation comprises LATIPS (large tilt-angle implanted punch-throughstopper) technique.
 10. A method for manufacturing a transistor on asemiconductor substrate, said method comprising the steps of: forming adielectric layer on said semiconductor substrate; etching saiddielectric layer to form an opening in said first dielectric layer;forming a gate oxide layer on said semiconductor substrate in saidopening; forming a barrier conductor along the surface of said opening;forming a metal layer on said barrier conductor and refilled into saidopening; removing a portion of said metal layer and said barrierconductor to form a gate for said transistor; removing said dielectriclayer; stropping said stripping said barrier conductor on sidewall ofsaid gate and forming under cut under said gate; forming sidewall spaceron sidewall of said gate; and forming lightly doped drain region is saidsemiconductor substrate by titled angle ion implantation; and formingsource and drain in said semiconductor substrate by ion implantationusing said gate and spacer as masking.
 11. The method of claim 10,wherein said dielectric layer comprises silicon oixde, siliconoxynitride, silicon nitride.
 12. The method of claim 10, wherein saidbarrier conductor comprises titanium nitride, tungsten, aluminum orcopper.
 13. The method of claim 10, wherein said metal layer comprisestitanium.
 14. The method of claim 10, wherein said titled angle ionimplantation comprises LATIPS (large tilt-angle implanted punch-throughstopper) technique.
 15. A transistor on a semiconductor substrate, saidmethod comprising the steps of: a gate oxide formed on saidsemiconductor substrate; a gate formed on said gate oxide, an under cutstructure being formed under said gate, wherein said gate is consistedof a barrier conductor and a main gate structure; spacer formed onsidewall of said gate and refilled into said under cut structure;lightly doped region formed in said semiconductor substrate, andadjacent to said gate; and source and drain formed in said semiconductorsubstrate, and adjacent to said lightly doped region.
 16. The transistorof claim 15, wherein said barrier conductor comprises titanium nitride,tungsten, aluminum or copper.
 17. The transistor of claim 15, whereinsaid main gate structure comprises titanium.
 18. A transistor on asemiconductor substrate, said method comprising the steps of: a gateoxide formed on said semiconductor substrate; a gate formed on said gateoxide, wherein said gate is consisted of a barrier conductor and a maingate structure; conductor spacer formed on sidewall of said gate;dielectric spacer formed on sidewall of said conductor spacer; lightlydoped region formed in said semiconductor substrate, and adjacent tosaid gate; and source and drain formed in said semiconductor substrate,and adjacent to said lightly doped region.
 19. The transistor of claim18, wherein said barrier conductor comprises titanium nitride, tungsten,aluminum or copper.
 20. The transistor of claim 18, wherein said maingate structure comprises titanium.
 21. The transistor of claim 18,wherein said conductor comprises spacer comprises titanium nitride,tungsten, aluminum or copper.